Telephonic Torture: First Hand Account
I am sitting on a chair reading Hindu and then I get a call. Expectantly I jump towards the phone only to find an unknown mobile number flashing on the yellow screen. Warlily I take up the call and things proceed as follows:
Caller (Hereafter called as C) : Hello, may I speak to Mr. Suharsh
Myself (Hereafter called as M) : Yes, this is Suharsh
C : Hi Suharsh, this is Deepak calling from...
M : (Interrupting)...yes..I received a call in evening.
C : So tell me something about what you have been doing on the job?
M : (Throwing lots of fundas,all false)...I have been involved in test case development, execution and code development using VHDL...we get specs from US and development happens according to them (Thinking: doing a stupid slave job)...
C : Which tool do u use for validation?
M : Mostly Modelsim (Thinking: God, now don't start asking about Modelsim, i know nothing...really..)
C : Ok...from your earlier call I gathered that you don't have much of industrial experience, would you mind if I ask u some basics in Digital?
M : (Thinking: Dear, thats all I know..please proceed)...Yes sure..
C : Ok, tell me what is Set up Time and Hold Time?
M : ...blah..blah..blah..
C : Can you tell me what happens if these are violated?
M : ...ok..Setup time is important as it governs the clock frequency...
C : (Interrupting)..I know that, but I want to know what will happen if its violated?
M :..Silent
C : (As if guessing that I don't know)..well I understand that it was a long time back and I won't mind if u say that u don't remember it...
M : (Thinking: Thanks for pulling me out of this morass)..well u r right, I know that, but the thing is that I have been mostly involved in functional validation (Read: Cut-Paste jobs) and therefore I have been out touch of timing aspects of designs lately.(Thinking : Actually, I have been just passing time at job, writing novels!!)
C : ..Ya I understand...Ok, have you ever done some system modelling using C?
M : (Thinking-C...?? System modelling? are u joking???)...No..But I have done my college project using System C (Thinking: College main toh bahut kuchh kiya tha beta)
C : Ok, so you have been into making test cases, can you tell me what is the structure of a test case..is it a text file or a program?
M : (Thinking: Probably he has understood that I have never even seen a test case!)..Well in my case its a .vhd file without a top level entity, it mostly contains stimulus in its architecture, which will fire the UUT and there is a mechanism to collect the output (Thinking-I really don't know what am I saying, so please excuse me!)
C : (A bit confused)...What is the difference between Variables and Signals in VHDL?
M : (Purana sawaal hai)..blah..blah..blah..
C : Thats ok, but can you tell me how do they relate to actual hardware?
M : (Thinking...Yaar till now u shud have known that I dont know anything, can't u spare me the blushes..!!)..Signals relate to ports and interconnections and variables...well I don't know about variables... (Thinking - lutwa lo apnee ijjat...)
C : Ok..variables actually relate to the wires in design..are you comfortable with 8085?
M : (Thinking: kya bol raha hai bhai, that was 6th semester and till now copy-paste has made my mind dumb)...that was a long time back..still I do know the basics and would try to answer your question..
C : Tell me how would you mask a TRAP interrupt in 8085?
M : (Thinking : Bomb shell marta hai baap...its great that I remember that TRAP is a non-maskable interrupt, is it necessary to ask further??)..I think TRAP is non-maskable...
C : Thats true, but can you build some hardware around it....
M : (Thinking: Kya hardware bhai, I don't even remember how does 8085 look like!!)...Not that I can think of..
C : ok..ok...I understand (Me thinking - u r so understanding!!)...can u tell me how to test a FIFO?
M : (Thinking: I remember FIFO, thats a big deal..and this mister wants how to test it, has he gone nuts??)...well its a first In first Out queue mechanism...first you can test that basic functionality is correct, i.e. give a set to stimulus and retrieve them to check that the order is expected...(Thinking- Please don't ask more..)
C : Ok...what else?
M : (Thinking : Kitna aur giraoge bhai!)...well then you may check the boundary conditions, i.e. addition when buffer is full and retrieval when its empty....
C : Ok..what else, you may time to think more if you want..
M : ( I roam about my room, looking at Sonia Gandhi in Hindu and answer)...I can't think of any more..
C : ok..ok..are you comfortable with C?
M : (Thinking : Chalo..at last..) Yes..
C : Wats the difference btw structure and Union?
M: Blah..blah..
C : (Sighs) Ok Suharsh, it was nice talking to u..Alok will get back to u soon regarding further stages, are u ready for further stages?
M : (Thinking : Thanks for saying this, as if u r really going to call me for further stages!!)..Yes sure..
C : Well then, Good Night ..Bye
M : Bye (thinking : Ah..Im safe now)
..and thus ended a 13.44 minute torture..
Caller (Hereafter called as C) : Hello, may I speak to Mr. Suharsh
Myself (Hereafter called as M) : Yes, this is Suharsh
C : Hi Suharsh, this is Deepak calling from...
M : (Interrupting)...yes..I received a call in evening.
C : So tell me something about what you have been doing on the job?
M : (Throwing lots of fundas,all false)...I have been involved in test case development, execution and code development using VHDL...we get specs from US and development happens according to them (Thinking: doing a stupid slave job)...
C : Which tool do u use for validation?
M : Mostly Modelsim (Thinking: God, now don't start asking about Modelsim, i know nothing...really..)
C : Ok...from your earlier call I gathered that you don't have much of industrial experience, would you mind if I ask u some basics in Digital?
M : (Thinking: Dear, thats all I know..please proceed)...Yes sure..
C : Ok, tell me what is Set up Time and Hold Time?
M : ...blah..blah..blah..
C : Can you tell me what happens if these are violated?
M : ...ok..Setup time is important as it governs the clock frequency...
C : (Interrupting)..I know that, but I want to know what will happen if its violated?
M :..Silent
C : (As if guessing that I don't know)..well I understand that it was a long time back and I won't mind if u say that u don't remember it...
M : (Thinking: Thanks for pulling me out of this morass)..well u r right, I know that, but the thing is that I have been mostly involved in functional validation (Read: Cut-Paste jobs) and therefore I have been out touch of timing aspects of designs lately.(Thinking : Actually, I have been just passing time at job, writing novels!!)
C : ..Ya I understand...Ok, have you ever done some system modelling using C?
M : (Thinking-C...?? System modelling? are u joking???)...No..But I have done my college project using System C (Thinking: College main toh bahut kuchh kiya tha beta)
C : Ok, so you have been into making test cases, can you tell me what is the structure of a test case..is it a text file or a program?
M : (Thinking: Probably he has understood that I have never even seen a test case!)..Well in my case its a .vhd file without a top level entity, it mostly contains stimulus in its architecture, which will fire the UUT and there is a mechanism to collect the output (Thinking-I really don't know what am I saying, so please excuse me!)
C : (A bit confused)...What is the difference between Variables and Signals in VHDL?
M : (Purana sawaal hai)..blah..blah..blah..
C : Thats ok, but can you tell me how do they relate to actual hardware?
M : (Thinking...Yaar till now u shud have known that I dont know anything, can't u spare me the blushes..!!)..Signals relate to ports and interconnections and variables...well I don't know about variables... (Thinking - lutwa lo apnee ijjat...)
C : Ok..variables actually relate to the wires in design..are you comfortable with 8085?
M : (Thinking: kya bol raha hai bhai, that was 6th semester and till now copy-paste has made my mind dumb)...that was a long time back..still I do know the basics and would try to answer your question..
C : Tell me how would you mask a TRAP interrupt in 8085?
M : (Thinking : Bomb shell marta hai baap...its great that I remember that TRAP is a non-maskable interrupt, is it necessary to ask further??)..I think TRAP is non-maskable...
C : Thats true, but can you build some hardware around it....
M : (Thinking: Kya hardware bhai, I don't even remember how does 8085 look like!!)...Not that I can think of..
C : ok..ok...I understand (Me thinking - u r so understanding!!)...can u tell me how to test a FIFO?
M : (Thinking: I remember FIFO, thats a big deal..and this mister wants how to test it, has he gone nuts??)...well its a first In first Out queue mechanism...first you can test that basic functionality is correct, i.e. give a set to stimulus and retrieve them to check that the order is expected...(Thinking- Please don't ask more..)
C : Ok...what else?
M : (Thinking : Kitna aur giraoge bhai!)...well then you may check the boundary conditions, i.e. addition when buffer is full and retrieval when its empty....
C : Ok..what else, you may time to think more if you want..
M : ( I roam about my room, looking at Sonia Gandhi in Hindu and answer)...I can't think of any more..
C : ok..ok..are you comfortable with C?
M : (Thinking : Chalo..at last..) Yes..
C : Wats the difference btw structure and Union?
M: Blah..blah..
C : (Sighs) Ok Suharsh, it was nice talking to u..Alok will get back to u soon regarding further stages, are u ready for further stages?
M : (Thinking : Thanks for saying this, as if u r really going to call me for further stages!!)..Yes sure..
C : Well then, Good Night ..Bye
M : Bye (thinking : Ah..Im safe now)
..and thus ended a 13.44 minute torture..
posted by Techie Author at 5:30 PM
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